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Example research essay topic: Floating Point Cost Efficient - 1,879 words

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The purpose of this paper assignment is to compare the Intel's IA- 32 Architecture with Sun UltraSPARC Architecture at a relatively broad level. First, I will introduce a brief history of each architecture family, and then follow that with a framework for making the comparison. Thereafter I will evaluate one product from each architecture family on the basis of the framework. In the conclusion I will state the preferred product and briefly summarize my reason for the choice. In the late 70 's, Intel introduced the Intel 8086 processor, and then quickly introduced the 8088 processor, which was more cost-effective. These were one of the first 16 -bit processors.

From there on, Intel's 32 -bit version was and still is the most popular because it offers a very wide range of applications. The 8086 processor was selected for IBMs PC (personal computer), which gave Intel the chance to broaden its horizon to develop a wide range of processors. These processors were based on a range of Complex Instruction Set Computing (CISC). CISC allows the number of bytes per instruction to vary according to the instruction being processed. It hard wires a set of instruction into a complex instruction. CISC uses variable length instructions, which increments by the length of the current instruction.

This CPU design philosophy is considered to be a poor due to the complexity of the design. The 8086 and 8088 introduced segmentation, which consist of a 16 -bit segment register containing a pointer to a memory segment of up to 64 Kbytes. They were also able to address up to 256 Kbytes without switching between segments using the four segment registers at a time. This allowed for a wide range of memory. But a 20 -bit address that is formed to use a segment register pointer and an additional 16 -bit pointer provides a total address range of 1 MByte, which allows for even more memory. Down the IA- 32 Architecture family came the Intel 286 or 80286.

This processor was significant because it introduced the protected mode. The protected mode uses segment register content as selectors or pointers into descriptor tables which provides a 24 -bit base address. This allows a maximum physical memory size up to 16 Mbytes for the support of virtual memory management and a variety of protection mechanisms. ] Intel 386 or 80386 processor was the next processor to be developed. The 80386 was the first 32 -bit processor, it introduced 32 -bit registers into the architecture. But it also maintained the properties of the 16 -bit register in order to provide complete backward compatibility. The 80386 also introduced a paging system, with a fixed 4 Kbytes size, which provided even more virtual memory management.

The IA- 32 architecture became a popular choice for advanced operating systems and a wide variety of applications due to the support of 4 Gbytes of virtual address space, memory protection and the paging support. The next in line was the Intel 486 processor or 80486. The 80486 processor was an expanded version of the 80386. The 80486 provided more transistors and ran at higher clock speeds.

It could execute one instruction per clock cycle rapidly. To increase the instructions that could be executed at a scalar rate of one per clock, an 8 Kbyte on chip first level cache (L 1) was added. This made memory access instructions to be included if the operand was in L 1. During this generation, the 80486 -clock processor doubled, allowing the processor to run at speeds 50, 66, and 75 megahertz (MHz).

In 1993 Intel introduced the Intel Pentium processor. This is the first processor out of the x 86 numbering series. The Pentium processor was known for its superscalar performance, which is an addition of execution pipelines. Performance in branch prediction, looping and internal data transfer speeds were improved, making this processor faster and a bit more manageable than the others.

The sixth generation of the Intel IA- 32 architecture is the Pentium Pro (with MMX technology). The most significant feature for the Pentium Pro is the integration of the processors second level cache memory (L 2) onto the processor module itself. Intel then started to make processors that were cost-efficient known as the Celeron and Xeon. These processors were more focused on the value of the PC market segment and other cost-efficient features. In 1987 Sun introduced the first SPARC (Scalable Processor Architecture) based computer, called the Sun- 4.

SPARC is a reduce instructions set computing (RISC) system using fixed length instructions. This means that the system was not as complex as the CISC system. SPARC introduced a series of processors throughout the years from Sun- 4 to SPARC 64, but one processor that standout the most is Suns 64 -bit UltraSPARC processor. The long awaited processor was designed to increase high performance at increased clock rates, range of price and scalability. UltraSPARC processor is the foundation for enhancement in other processors. UltraSPARC architecture is persistent on its open availability, believing that it is the key to technological success.

The Intel processors are known for their backward compatibility. Included in their 32 -bit registers are previous generations of 16 -bit registers. They also combine IBM and DOS to insure that each new generation would run software developed for the previous chip. The backward compatibility of Intel processors furthermore helps protect their customers large investment in software.

Intel's framework consists of six main stage of the IA- 32 architecture. The first is the bus interface unit, this accesses memory and input and output (I/O) for other units. Second is the code prefetch unit, which receives object code from the bus unit and puts it into 16 -byte. Next is the instruction decode unit, it decodes an object code from the prefetch unit into a microcode. Then the execution unit executes the microcode instruction in order for the segment unit to convert logical to linear addresses and provides protection check. The final stage is the paging unit; this stage is the same as the segment unit with the exception for page based protection check and contains a cache with information for up to 32 most recently accessed pages.

Intel's memory is based on both flat and segmented memory. It was able to provide up to 4 Gbytes of physical memory. Then with the Intel 386, they developed a paging system, mention earlier, which had a fixed 4 -kbyte size to provide a method for virtual memory management. The paging system was more efficient for operating systems and it did not have to sacrifice the execution speed. On a scalar level, Intel incorporated their execution units into five-pipelined stage. Each stage operates in parallel with the others on and up to five instructions in different stages of executions.

Therefore the processor is able to rapidly execute one instruction per clock cycle. Then an 8 -Kbyte on-chip first level cache was added to increase how many instructions that could be executed at a scalar rate of one per clock. Second level- cache was also added, but that only complicated the systems and much more powerful. Furthermore, Intel added a second execution pipeline to achieve superscalar performance. These features enhanced Intel processors performance in speed. For Intel's processor scalability, they developed a technology called MMX.

MMX technology uses single-instruction, multiple data (SIMD) execution model, this helps the 64 -bit MMX register to perform parallel computations on packed integers. The main feature of this technology was to improve the performance of their advanced media, data compression applications and image processing. Intel also developed Streaming SIMD Extensions, this provided a new set of 128 -bit registers and helped to perform SIMD functions on packed single-precision floating-point values. After SSE, came Streaming SIMD Extension 2 (SSE 2). This new technology consists of new floating-point SIMD instructions, which allows computations to be performed on packed double-precision floating-point values. The SSE 2 provide more flexibility and higher dynamic range of computational power by supporting more data.

SPARC architecture includes the integer unit (IU) also known as the CPU, and the floating-point unit (FPU). But for UltraSPARC-IIi, they designed the Integer Execution Unit (IEU). The IEU provides maximum performance while maintaining full software compatibility, minimizing processor architectural changes to host software. The FPU is a pipelined floating-point processor.

It consists of five separate functional units to support floating-point and multimedia operations. This allows the processor to execute two floating-point instructions per clock cycle. SPARCs pipeline strategy is a double-instruction-issue with nine stages: fetch, decode, grouping, execution, cache access, load miss, integer pipe wait, trap resolution and write back. Therefore nine instructions can execute concurrently at one clock per cycle. Three other stages were added to the pipeline making it even with the floating-point pipeline, making pipeline synchronization and exception handling simpler. UltraSPARC is well known for their scalability, which allows implementations through a range of price and performance levels, with its high bandwidth bus support and register window design.

A processor must support branching in order for reasonable computational tasks to be handled. UltraSPARC uses dynamic branch prediction to speed the processing of branches, which speeds up the execution process and is highly efficient for looping branches. Their cache architecture helps to reduce bus traffic and increase system throughput. There are three parts to this architecture, which includes data cache, instruction cache and external cache. Each cache system supports the other on a tagged basis. Like Intel's MMX technology, UltraSPARC developed their Graphics Unit, which provides strong support for advanced graphics and multimedia operation requiring high performance.

I think UltraSPARC architecture is targeted to all aspects of computer users. Their high performance is attractive to business and workstations, while their low cost and performance is attractive to home users and small businesses. I also believe this is true for Intel IA- 32 architecture. For Intel, they offer a series of processors that can accommodate different users.

For instance, their more complex Pentium III might be more useful to larger companies then say their cost efficient Celeron processor. I also think that both Companies will last in the future. They both have improved their technologies at their own pace and I believe they will keep making improvements as the years go by. From the above comparison I think that Suns UltraSPARC architecture is infinitely superior to product because it outperforms Intel IA- 32 architecture on four of the five criteria of my framework.

Sun uses a RISC system, which is far less complex than Intel's CISC system. The UltraSPARC processor scalability outweighs Intel processors by a wide range of semiconductor technologies, chip implementations and system configurations. An integration of cache, memory management, and floating-point units, allows the UltraSPARC processor to be produced at price and performance levels suitable for systems ranging from laptops to supercomputers. UltraSPARC cache system is more efficient than Intel's cache system because of their combination between data cache, instruction cache and external cache. UltraSPARC performance level is a cost efficient level. The open availability is Ultra SPARCs main key, because they believe it is critical to the success of technology.

UltraSPARC is persistent that all their architecture is open to those who would like their design. This makes UltraSPARC systems to become evolutionary. References web web web web IA- 32 Architecture. pdf web web


Free research essays on topics related to: floating point, memory management, virtual memory, cost efficient, wide range

Research essay sample on Floating Point Cost Efficient

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