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Research Statement Current Research The Areas and Future Projects of my Research My research interests cover the areas of embedded system designs, computer architectures and computer-aided design. My research emphasizes on system-level design methodologies, verification of embedded system designs, and architecture modelling and exploration. The topicality of my research interests is determined by the fact that today the traditional design methods and techniques are no longer efficient. This happened because embedded systems became increasingly complex. More than ever, design and verification methodologies at higher levels of abstraction are required to minimize the design cost of electronic products.
To make the practice of designing from high-level system specification a reality, new design technologies have to be developed to accompany every step in the design flow. These technologies should at least include design specification, simulation, verification, synthesis, and design exploration. In my dissertation research, I focused on verification methods and design exploration techniques for system level designs, and also actively worked on the research and development of a next generation design tool set Metropolis [ 1 ]. In the future, I plan to initialize research directions in design for: Verifiability (verification-driven design specification approach), System level synthesis (it connects the system level design specification to the lower level implementation), High-level architecture modeling (it enables architecture exploration and verification at a higher level of abstraction).
Along with the previous work on the verification methods, these technologies together will achieve an integrated design methodology that will be able to overcome the challenges from the increasing design complexity. The Goals and Achievements of my Current Research I have worked on the verification methods for embedded system designs at multiple levels of abstraction. I proposed a formal verification methodology for system designs at multiple levels of abstraction and achieved the following results: An existing software formal verification tool is utilized as the backend verification engine An automatic translation mechanism from system specifications at multiple levels of abstraction to lower level verification models is developed The verification-driven design refinement is enabled. By implementing this methodology, a verification backend tool was integrated in the Metropolis environment and its usefulness and effectiveness was demonstrated through several case studies. Now I am working on a research project for automatic design abstraction, abstraction propagation and design specification for abstraction. The necessity of this project is determined by the fact that up until now, the process of design abstraction (i.
e. the simplification of the design) has been done by hand or left to the verification tools as they explore the reachable states and analyze the properties. The goal of this research direction is to not only automate the verification process, but also automate or semi-automate the simplification of the verification problem. Another main research direction in my dissertation is assertion-based simulation verification. I proposed a simulation verification methodology based on trace analysis and automatic trace checker generation. The methodology begins with the formal specification of LOC or LTL properties, automatically generates runtime monitors or static checkers for trace analysis, checks the simulation traces during or after the simulation, and reports design errors if there is any property violation.
I mentored a graduate course project that exercised the methodology I proposed on low power techniques in network processor architectures, and the results were successful [ 2 ]. Future Research Proposal My future research goal is to develop new design and verification methodologies to accelerate the productivities of the semiconductor industry. Design methodologies at higher levels of abstraction will become a must due to the gap between the increasing semiconductor manufacturing capabilities and the limited design productivities [ 3 ]. To achieve my research goal I will investigate and apply my methodologies in the following several directions: Design for verifiability.
It is a verification-driven design approach at the system level. In current design technologies, designers are usually given full flexibility to specify a system design, which makes the verification extremely difficult and costly. Since verification has become the dominant cost in the current design process, the design flexibility has to be compromised to improve the verifiability and therefore reduce the overall design cost. To make this approach practical and useful, the tradeoff between design flexibility and verifiability will be carefully studied. And a systematic and hierarchical design specification method will be proposed according to the verification methods. System level synthesis.
It is a key step in the system level design that connects the system specification to the lower level implementation. At the system level, many design requirements, such as timing and power, are abstracted as constraints without considering their implementation. High-level synchronization constructs are used to coordinate the concurrency. These abstract constraints and synchronization constructs need to be synthesized into concrete scheduling units in hardware or algorithms in software as the design is refined to lower level implementation.
A library-based synthesis approach will perhaps be one of the solutions. In addition, the validation between different levels of abstraction in the synthesis is also an open topic that needs to be investigated. High-level architecture modelling. It is an important technology for platform-based design, and it will enable efficient exploration and verification for architectural platforms at a higher level of abstraction. Platform-based design was proposed to facilitate the design reuse and architecture-function separation in the context of system level design. In platform-based design, a flexible architecture modelling method at the system level is necessary to allow design exploration and software / hardware co-verification at an early design stage without much lower level design details.
My future research plans also cover the direction which combines simulation and formal verification techniques in the system level verification. From a current project of system level deadlock detection, the latest results of which were submitted to DAC 05 (the premium conference in embedded systems and design automation), it was observed that formal verification and simulation verification should be able to complement each other quite well at the system level due to their advantages on verification thoroughness and efficiency respectively. Though semi-formal verification techniques have been proposed in the literature, a practical solution for system level designs is missing. The goal of this direction is to propose a unified verification methodology for system level designs in a practical way by combining the two verification methods. Formal verification and simulation verification techniques will be used together to make system level verification both efficient and highly confident. In my research, I have been closely collaborating with other researchers from both industry and academia.
The senior researchers in Cadence Berkeley Laboratories provided me with invaluable comments for many of my papers, and inspired me in various research projects. In summer 2004, I visited University of California, Berkeley, and collaborated with the VLSI CAD group led by Prof. Alberto San giovanni-Vincentelli. At UC Berkeley, I got the precious opportunity to work on the release of Metropolis 1. 0 by getting my backend verification tools integrated in this system level design environment. While collaborating with the researchers there, I initialized new research projects and directions in system level deadlock detection, architecture modeling, and refinement and implementation checking. I will keep the cooperative connections with these outside researchers and research groups, and turn the new ideas and directions into solid research projects.
Under the supervision of Prof. Harry Hsieh, I have accumulated research visions and capabilities throughout the years of exposure to the academia. I am confident to become an independent researcher, though I have to continuously improve my abilities in initializing new and breakthrough research topics. References: F. Balarin, H. Hsieh, L.
Lavagno, C. Passer one, A. Sangionvanni-Vincentelli, and Y. Watanabe, "Metropolis: An Integrated Electronic System Design Environment", IEEE Computer, 6 (4), pp. 45 - 52, April 2003. J.
Yu, W. Wu, X. Chen, H. Hsieh, J.
Yang, and F. Balarin. "Assertion-Based Design Exploration of DVS in Network Processor Architectures", to appear, in Proceedings of Design Automation and Test in Europe (DATE ' 05), Munich, Germany, March, 2005. web 2004.
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